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ASIC Packaging Signal/Power Integrity Hardware Engineer (Hybrid)
Cisco · San Jose, CA · Posted 36 days ago
Design high-speed ASIC packages that carry over 90% of global IP traffic across Cisco's unified silicon architecture.
The application window is expected to close on: 12/30/2026 This position requires that you live within commuting distance of our San Jose, CA office and commute to the office at least 4-5 days per week.
Cisco Silicon One (#CiscoSiliconOne) is a business organization with a long track record of building complex and high-performance Silicon ASICs. Our silicon devices drive the world’s most complex networks and carry over 90% of IP traffic. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.
We are a highly specialized ASIC team with experts in all aspects of advanced IC package design and heterogeneous system integration. Our substrates use the latest 2.5D fanout technologies for large-scale integration, using the latest signaling and data transfer technologies. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry!
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This role is one of 14 Hardware Engineer openings in San Jose, CA and centers on Signal Integrity, Power Integrity, High-speed Design, and Transmission Line Theory. There are 1,188 open roles at Cisco right now.
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