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Principal Subsystem Design Manager
Microsoft · Raleigh, NC · Posted 97 days ago
The AISoC silicon team is seeking a Principal Subsystem Design Manager to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. Build, hire, and mentor a team of engineers, supporting their career growth and professional development. Manage a Subsystem design team with focus on architectural and micro-architectural based functions and features. Technically lead one or more Subsystems. Interact with architects to develop micro-architectural specifications and work with DV engineers to execute them. Collaborate across teams on vertical and horizontal reuse of components. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Provide technical leadership through mentorship and collaboration. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Equivalent Experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. …
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There are 1,743 open roles at Microsoft right now. This role centers on Digital Logic Design, Microarchitecture, Verilog, and Systemverilog.
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