Principal Subsystem Engineer (Design or DV)

The AISoC silicon team is seeking a Principal Subsystem Engineer (Design or DV) to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. Team is currently looking for subsystem design and DV leads. Technically lead one or more Subsystems as a design or DV engineer. Collaborate across teams on vertical and horizontal reuse of components. Provide technical leadership through mentorship and teamwork. Work effectively with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up. Deep understanding of many of the following: complex subsystems (such as PCIE, HBM, imaging or control), fabrics, AMBA AXI/CHI protocols, DMA engines, NoCs, and high-throughput data buffering and movement. Design includes but not limited to - Bandwidth, latency, utilization, and power tradeoffs while driving synthesis, timing constraints, floor-planning awareness, and performance tuning (Design). Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. …

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