Systems Verification & Concurrent Kernel Architecture Research Intern

The Mission Transitioning a kernel from a monolithic "Big Kernel Lock" to fine-grained concurrency is a high-risk engineering challenge. Traditional testing is mathematically incapable of catching the non-deterministic "Heisenbugs" inherent in parallel execution. This internship is a 3-month intensive study to determine the practical limits of using automated formal methods to guarantee the safety of concurrent kernel primitives.

The Challenge: The "Logic-to-Silicon" Gap You will navigate the intersection of low-level systems grit and formal rigor to bridge three volatile domains: Concurrency: Managing state-space explosion when multiple cores access shared kernel objects simultaneously. Memory Models: Ensuring locks respect the weak consistency and instruction reordering of ARMv8/ RISC-V hardware. Automated Proof: Using SMT-based tools to achieve high-assurance "push-button" verification without the years-long overhead of manual theorem proving.

Roles and Responsibilities

• Design Logic (TLA+/Spin): Formalize locking protocols to mathematically prove the absence of deadlocks and circular waits.
• Implementation Audit ( ESBMC / CBMC ): Apply Bounded Model Checking to C source code to exhaustively scan for data races, pointer safety, and invariant violations.
• Hardware Mapping: Verify the placement of memory barriers to prevent hardware-level synchronization failure on modern CPUs.
• AI-Augmented Scaling: Leverage LLMs as an "Inference Engine" to synthesize formal invariants and environment harnesses, then critically audit the results for logical soundness.

Qualifications

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