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Advanced Substrate Design & Process Integration

AMD · Austin, TX · Posted 2 days ago

unknown
Substrate designDesign rulesStack-up designRouting architectureHDI designAdvanced package substratesDesign for manufacturabilityDesign for yield

THE ROLE Lead the development of next-generation substrate architecture, design rules, and technology platforms that enable AMD's future packaging solutions. This role focuses on substrate design enablement, process integration, design-for-manufacturability (DFM), design-for-yield (DFY), reliability, and electrical performance optimization. This role is for a seasoned engineer to define substrate technology requirements and design methodologies that bridge product needs with manufacturing capabilities. You will work closely with package architects, substrate designers, silicon teams, and manufacturing partners to co-optimize substrate solutions for performance, yield, reliability, and cost.

THE PERSON The ideal candidate is a technical leader with deep expertise in substrate design architecture, process integration, substrate manufacturing technologies, and package-system co-design. They have developed substrate design rules and technology platforms used in advanced semiconductor products. They understand the tradeoffs between electrical performance, mechanical reliability, manufacturability, and cost, and are skilled at translating product requirements into scalable substrate technologies.

KEY RESPONSIBILITIES Substrate Architecture & Design Rule Development

  • Define substrate technology requirements and design roadmaps for future AMD products.
  • Develop substrate design rules, stack-up methodologies, routing architectures, and technology guidelines.
  • Establish scalable design infrastructures supporting future substrate technology nodes.
  • Drive substrate architecture development across line/space scaling, via technologies, and advanced package integration.

Process Integration

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There are 1,335 open roles at AMD right now. This role centers on Substrate Design, Design Rules, Stack-up Design, and Routing Architecture.

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