# AI/ML Silicon Accelerator Memory Architect

### Memory Subsystems and Low-Power Data Transport **Level:** Principal Architect/Distinguished Architect **Function:** Silicon Architecture — AI/ML Accelerators --- ## The Role You will define the end-to-end memory *and* data transport architecture for our accelerators — from the memory technology we bet on, through the controller, on-die network, and DMA engines, all the way into the scratchpads feeding the compute blocks. This is not a "pick the DRAM generation" role. It is ownership of the whole data path across multiple silicon generations, including the performance-versus-power analysis that decides major trade-offs and the co-architecture with internal teams and external memory/IP vendors. --- ## What You'll Own **Memory architecture and roadmap.** Multi-generation memory strategy across the portfolio — HBM, LPDDR/GDDR/DDR, on-die SRAM hierarchies and scratchpads. Capacity, bandwidth, and latency requirements derived from real AI workloads (model size, KV-cache growth, prefill versus decode, MoE sparsity). Memory controller and cache/scratchpad microarchitecture: scheduling, address mapping, QoS across compute, DMA, and host traffic. **Data transport and energy-efficient movement.** The complete path from memory to the MACs: on-die interconnect (topology, flow control, deadlock avoidance, QoS under mixed traffic), and the DMA, gather/scatter, layout-transform, and multicast engines that make it usable. You own the pJ/bit budget as a first-class constraint. **Modeling and silicon realization.** Analytical and simulation-based models that make architectural calls with quantified confidence. ## Minimum Qualifications

• MSEE/MSCE or PhD in EE, CE, CS, or related field, or equivalent demonstrated

architectural impact.

• 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or

AI. Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR, controller architecture, cache coherency and memory consistency models, tiered and pooled memory.

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