Get roles like this, scored and matched, in your inbox.
Sign up free →Job Opening
ASIC Digital Design Manager
Ansys · Posted today
Lead a team building Ethernet MAC and PCS controllers for networking silicon in data centers, automotive, and AI systems, with ownership of design reviews, timing closure, and hiring.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are You have spent a decade building IP that ships, not just passes verification. You know that the best microarchitecture is the one that survives contact with timing closure, power constraints, and the realities of a 5nm process node. You have been the person in the room who catches the CDC issue before it becomes a silicon respin, and you have learned that the hardest part of leading a design team is not writing the cleanest RTL, it is teaching five engineers to think three steps ahead without micromanaging their every line of code. You are equally comfortable reviewing a timing report at 9 a.m. and having a career conversation with a junior engineer at 3 p.m. You do not just manage projects, you grow people. When someone on your team hits a wall on a complex AXI bridge implementation, you know when to step in with technical guidance and when to let them work through it. You have strong opinions about what makes good SystemVerilog and you are not afraid to push back when an architecture decision does not make sense for the product or the schedule. At Synopsys, you will lead a team building Ethernet MAC and PCS controllers that power networking silicon across the industry. The work is technically hard, the team is real, and what you build will matter.
What You'll Be Doing
…
This posting is sourced from Ansys's own career site — applying takes you there directly.
Get roles like this, scored and matched, in your inbox.
Sign up free →Related roles
This role centers on Systemverilog, Verilog, Rtl Design, and Microarchitecture. There are 6 open roles at Ansys right now.
See this month's Hiring Index: Fabs Are Closing. Design Isn't. for the broader trend behind roles like this one.
Want roles like this found for you?
Set your Focus once. Career Engine screens every new opening every week.
A scored, explained shortlist — not a keyword match — delivered weekly. Free for one profile.