ASIC Timing Engineer

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

ASIC Timing Engineer

Etched is seeking an exceptional ASIC Timing Engineer to join our innovative team. The candidate will be responsible for driving timing analysis and closure of our next-generation AI chips, ensuring that we meet the high-performance demands of our unique architecture.

Representative Projects:

• Drive timing analysis and closure of chips at block, cluster, and full chip level
• Collaborate with Physical Design, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, and ensure timing and power convergence, as well as ECO implementation
• Enhance timing convergence flows in partnership with our methodology teams
• Contribute to DFT logic understanding and assist with DFT timing closure for various modes, such as scan and BIST
• Work on timing closure of digital logic/macros in AMS designs/IPs, ensuring all aspects are addressed

You maybe a good fit if you have:

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