CPU Design Verification Engineer II

About the Role You'll verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout. This is a hands-on role at the block and core level: you'll write testbench components, build constrained-random and directed stimulus, close coverage, and debug the hard failures that come out of nightly regressions — pipeline hazards, memory-ordering violations, speculation and flush corner cases, and co-simulation divergences between RTL and the golden ISA model. You'll work directly with core micro-architects and RTL designers, and you'll own verification of specific units (e.g. rename/dispatch, issue queues, load-store unit, MMU/TLB, branch prediction, or the retire/commit path) as well as core-level scenarios.

What You'll Do

• Own the verification plan for one or more OOO core units: extract testable features from the micro-architecture spec, define stimulus and coverage requirements, and drive them to closure.
• Build and extend UVM testbench infrastructure — agents, drivers/monitors, scoreboards, reference models, functional coverage, and assertions (SVA).
• Develop constrained-random test generators and directed tests (C/assembly test programs plus SV stimulus) targeting deep pipeline states: speculative execution and misprediction recovery, replay and livelock scenarios, exception/interrupt injection, memory-ordering and coherence corner cases, and privilege/virtual-memory transitions.
• Debug regression failures end to end: triage waveforms, correlate RTL state against instruction-by-instruction co-simulation mismatches (PC, write-data, CSR state), and reduce failures to a minimal reproducer with a clear root-cause writeup for the designer.
• Drive coverage closure — code, functional, and assertion coverage — including analyzing holes, adding stimulus or coverage waivers with justification, and reporting progress against tapeout milestones.
• Maintain and improve regression health: keep failure signatures triaged and bucketed, reduce noise, and improve turnaround time and debuggability of the test flow.
• Contribute to the verification environment and tooling: build/run flows, log parsers, failure-signature classification, and CI integration.
• Review micro-architecture and RTL changes for verification impact; participate in spec reviews and file spec ambiguities.

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