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Job Opening

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Design Engineer

Altera · Bengaluru, Karnataka · Posted 7 days ago

ic
3+ yrs expRTL designSystemVerilogVerilogFPGASoCStatic timing analysisTiming closureClock domain crossing

Job Description: Altera is seeking a highly motivated Design Engineer to contribute to the development of cutting-edge FPGA and SoC solutions. In this role, you will be involved in the full design lifecycle, from concept to silicon, ensuring high-quality and high-performance products.

Job Responsibilities:

  • Perform RTL design, verification, and synthesis of complex digital circuits for FPGA and SoC products.
  • Develop and execute comprehensive test plans and verification environments using industry-standard methodologies.
  • Collaborate with architecture, validation, and software teams to define specifications and ensure design integrity.
  • Analyze and debug design issues, performing root cause analysis and implementing effective solutions.
  • Optimize designs for performance, power, and area targets.
  • Participate in design reviews and contribute to continuous improvement of design methodologies and processes.
  • Generate design documentation, including specifications, test plans, and release notes.
  • Preferred to have system level understanding
  • Proficiency with System Verilog and RTL coding skills,  timing closure, or STA, targeting high performance designs·
  • Very good understanding of latest protocol specifications for memory, bus protocol specification like AXI, PCIe and Ethernet interfaces, Security IPs (for ex: MACSec)·
  • Experience with FPGA tools and timing closure
  • Hardware power-on and debug·
  • New product release and rollout support·
  • Customer technical support

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in digital IC design, with a focus on RTL design and verification.
  • Proficiency in Verilog or SystemVerilog for RTL design and testbench development.
  • Experience with industry-standard EDA tools for simulation, synthesis, and static timing analysis.

Strong understanding of digital design fundamentals, including clock domain crossing (CDC) and reset synchronization.

…

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There are 211 open roles at Altera right now. This role centers on Rtl Design, Systemverilog, Verilog, and Timing Closure.

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