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Design Engineer
Cadence Design Systems · Shanghai, Shanghai · Posted 8 days ago
Own custom layout floorplanning and high-speed mixed-signal PHY layout (SerDes, USB, DDR) at Cadence, working hand-in-hand with the analog design team.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Custom Layout Design Engineer
Position Description:
- Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
- Responsible for custom layout top level hierarchy floorplan for blocks/powers
- Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
- Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.
Position Requirements:
- BSEE degree with 2+ years of applicable experience in analog/custom layout of advanced technology nodes
- Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
- Proficient with EMIR tools, like Voltus-FI
- Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
- Fundamental understanding of IC design technology and process/methodology
- Essential that the individual demonstrates good teamwork and self-motivation
- Good communication skills in English
- Work experience in PERC run is a plus
- Work experience in FinFET layout is a plus
- Work experience in ESD/Latch-up is a plus
- Work experience in cooperation with digital P&R team is a plus
This posting is sourced from Cadence Design Systems's own career site — applying takes you there directly.
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