DFT Engineer

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools—you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

• DFT Architecture & Strategy

• Be part of the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support

• Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards

• Design and implement DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG for high-end devices

• Test Pattern Development & Optimization

• Generate and optimize high-quality test and debug patterns for production
• Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
• Drive test coverage and quality metrics to meet stringent manufacturing requirements

• Cross-Functional Collaboration & Methodology Innovation

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