Career EngineCareer Engine
Your matchExample
74%match
Why you fitThis role calls for Physical Design and Placement And Routing — tell us what you know and we'll check the rest.
Gap to noteAlso lists Clock Tree Synthesis — worth confirming before you apply.

Get roles like this, scored and matched, in your inbox.

Sign up free →

Job Opening

Intel logo

EDA Tools Hardware Engineer

Intel · Santa Clara, CA · Posted 96 days ago

$142k–$269khybridic
Physical DesignPlacement and RoutingClock Tree SynthesisFull-Chip IntegrationInnovusStatic Timing AnalysisPower Grid DesignIR Drop Analysis

Job Details:

Job Description: The Role and Impact Join Intel's world-class team as an EDA Tools Hardware Engineer, where you will play a pivotal role in shaping the future of silicon innovation. This position directly contributes to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies. Your work will enhance the efficiency of design processes and optimize power, performance, and technology node advancements. As part of Intel, you will have the unique opportunity to collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations that enrich lives worldwide.

Key Responsibilities

  • Full Chip Implementation Flow Development
  • Develop and maintain full-chip physical implementation flows including:
  • Floor planning and partitioning strategies
  • Hierarchical block integration
  • Chip-level placement and routing coordination
  • Power grid planning and analysis
  • Clock tree synthesis (CTS) strategy integration
  • Enable scalable SoC assembly flows for multi-block and multi-power domain designs.
  • Define methodology for hierarchical design reuse and integration

Qualifications: Minimum Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field with 6+ years of experience; or a Master's degree with 4+ years of experience; or a PhD with 2+ years of experience
  • Physical design fundamentals (I.e. placement, routing)
  • Clock tree synthesis (CTS)
  • Full-chip integration methodologies using Innovus

Preferred Qualifications

  • Static timing analysis (STA)
  • Power grid design and IR drop concepts
  • Experience with large SoC or multi-block design implementation flows
  • Experience scripting and automation skills in Linux environments

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

…

Apply on Intel's site →

This posting is sourced from Intel's own career site — applying takes you there directly.

Get roles like this, scored and matched, in your inbox.

Sign up free →

Related roles

There are 928 open roles at Intel right now. This role is one of 13 Hardware Engineer openings in Santa Clara, CA and centers on Physical Design, Placement And Routing, Clock Tree Synthesis, and Innovus.

See this month's Hiring Index: Fabs Are Closing. Design Isn't. for the broader trend behind roles like this one.

Want roles like this found for you?

Set your Focus once. Career Engine screens every new opening every week.

A scored, explained shortlist — not a keyword match — delivered weekly. Free for one profile.