Front-End Power Engineer

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Key responsibilities

• Optimize RTL designs to boost power efficiency while meeting performance and area objectives.
• Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling.
• Conduct power estimation and evaluate PPA trade-offs for both new and existing design features.
• Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases.
• Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions.

You may be a good fit if you have

• Experience in RTL development using Verilog/SystemVerilog, with a focus on low-power RTL design and optimization for complex digital systems.
• In-depth knowledge and experience in implementing low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS).
• Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power.

Strong candidates may also have experience with

• UPF/CPF power intent specifications.
• Power analysis tools such as Synopsys PrimePower, Cadence Joules, or similar.
• Automation of power analysis and optimization workflows using scripting languages (Tcl, Perl, Python).

Benefits

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