GPU Logic Design Engineer

Job Description: The Role and Impact As a DFT Design Engineer, you will play a crucial role in developing and delivering high-quality design-for-test (DFT) solutions for cutting-edge semiconductor products. You will focus on logic design, RTL coding, and simulation, while collaborating on architecture and microarchitecture definitions. Your contributions directly impact product quality and manufacturability by optimizing test coverage, debug efficiency, and production ramp-up, ensuring Intel's leadership in advanced SoC designs.

Business group The Data Center Group (DCG) drives innovation in data center technologies to empower businesses and industries globally. As part of this high-impact organization, you will contribute to the development of world-class systems and solutions that support Intel's vision to transform data into actionable insights, enabling scalable, efficient, and secure computing.

Key Responsibilities

• Develop logic design, RTL coding, and DFT timing closure support for test content generation, including SCAN, MBIST, and BSCAN.
• Collaborate on the definition of architecture and microarchitecture features for blocks and subsystems under DFT design.
• Create and optimize HVM content for rapid bring-up and production ramp on automatic test equipment (ATE).
• Apply strategies, tools, and methods to integrate DFT into RTL and structural code while meeting power, performance, area, and timing goals.
• Review verification plans and drive verification of DFT designs to ensure alignment with architecture and microarchitecture specifications.
• Resolve RTL test failures and implement corrective measures to ensure design accuracy and feature correctness.
• Integrate DFT blocks into functional IP and SoC, supporting SoC customers to ensure seamless integration and high-quality design outcomes.
• Collaborate with post-silicon and manufacturing teams to support debug and verification on silicon, documenting learnings for continuous improvement.
• Drive high test coverage and develop structural and specific IP tests to achieve quality and defect-per-million (DPM) objectives.

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