Manager, Design Eng (Design Verification)

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Inviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s RnD team has embarked upon to date. As part of our team, you will have the opportunity to take the lead on and contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of IP designs. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, knowledge on Serial protocols, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc. You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art methodologies.

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