Memory Design Engineer

Job Description: Intel's Corporate Memory Organization (CMO) within Design Technology Platform (DTP) drives development of Memory Compilers on Intel's leading-edge process technologies. The organization is responsible for architecting, designing and delivering high-performance and energy-efficient embedded memory IP that maximize silicon performance, optimize density, and maximize manufacturing yield across Intel Products and Intel Foundry platforms.

As a Circuit Design Engineer in CMO, you will be responsible for architecting, designing, and delivering SRAM compilers across high-density (HD) and high-performance (HP) profiles. You will also collaborate with Intel’s Technology Development (TD) group on Design and Technology Co-Optimization (DTCO) to co-define the silicon process and physical layout rules.

Responsibilities of the role include but are not limited to:

• Provide industry competitive SRAM design solutions to meet challenging memory design specs for various product segments.
• Design, validation, and characterization of Memory Compilers.
• Memory Compiler Design Flow and Methodology development.

Behavioral skills/traits as follow:

• Interfacing with customers.
• Logical thinking, analytical and problem-solving skills.
• Verbal/written communication skills.
• Interpersonal skills.
• Multitasking/prioritization skills.

This is an entry level position, and compensation will be given accordingly.

Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience or coursework listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

This position is not eligible for Intel immigration sponsorship.

Minimum Qualifications:

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