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Network Site Reliability Engineer, Senior Staff AI Solutions Lab
Marvell Technology · Santa Clara, CA · Posted 8 days ago
Own the compute and software foundation of Marvell's AI Solutions Lab, building and operating the GPU/HPC clusters that validate CPO, CXL, and Teralynx systems before hyperscaler customers see them.
Your Team, Your Impact
The Solutions Architecture team sits within Marvell's Platform organization, which turns advanced silicon into deployable, customer-ready AI and cloud infrastructure. This team — the AI Solutions Lab — owns the validation layer that proves our platforms perform as promised, across compute, networking, and memory fabrics. Without it, Marvell could design great silicon but could never prove, at rack scale, that it performs the way customers expect — and hyperscalers don't buy chips on paper, they buy validated systems.
Day to day, the team runs AI benchmarking experiments that mirror real customer workloads, operates GPU/HPC lab clusters, validates Marvell's Teralynx switching and AI fabrics under production-like conditions, and builds live demos for trade shows — carrying platform programs from concept to production.
What sets this team apart is breadth of ownership: engineers here aren't limited to validating a single switch chip — they work across the full breadth of Marvell's AI platform portfolio, from Teralynx network fabrics to integrated optical platforms like co-packaged optics (CPO) and near-packaged optics (NPO), as well as emerging memory fabric products such as CXL and photonic fabric memory appliances. This cross-domain ownership — networking, optics, and memory, together — is work that's often siloed across separate teams elsewhere, and the results feed directly into customer proof points and executive reviews. What You Can Expect The NRE/SRE Engineer owns the compute and software foundation of the AI Solutions Lab. This role is responsible for building, standardizing, and operating the environments required to validate Marvell solutions across customer-relevant workloads, including scale-up, scale-out, memory acceleration, and DPU-enabled use cases.
Key Responsibilities
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