Principal DFT Engineer

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle—from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.

This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.

Key Responsibilities

DFT Architecture & Technical Leadership

• Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies

• Lead DFT planning, specification, and quality tracking across the project lifecycle

• Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout

Execution Across the Full Lifecycle

• Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels

• Own end-to-end DFT activities from specification through silicon bring-up and production support
• Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements

Methodology & Cross-Functional Impact

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