Get roles like this, scored and matched, in your inbox.
Sign up free →Job Opening
Principal PCS/PMA RTL Design Engineer
Astera Labs · San Jose, CA · Posted 2 days ago
Build PCS/PMA digital logic for Ethernet, PCIe, UCIe, and UALink in AI and cloud connectivity ASICs, from RTL through tapeout and silicon bring-up.
Principal PCS/PMA RTL Design Engineer
Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs.
You will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation.
This is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure.
Key responsibilities
PCS/PMA RTL design and implementation
…
This posting is sourced from Astera Labs's own career site — applying takes you there directly.
Get roles like this, scored and matched, in your inbox.
Sign up free →Related roles
This role centers on Verilog, Systemverilog, Rtl Design, and Digital Asic Design. There are 191 open roles at Astera Labs right now.
See this month's Hiring Index: Fabs Are Closing. Design Isn't. for the broader trend behind roles like this one.
Want roles like this found for you?
Set your Focus once. Career Engine screens every new opening every week.
A scored, explained shortlist — not a keyword match — delivered weekly. Free for one profile.