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R&D Engineering, Sr Engineer
Synopsys · Seongnam Si · Posted 3 days ago
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are You have spent years in the trenches of physical design, where the difference between a chip that tapes out clean and one that needs a respin often comes down to a timing path you caught at 2 AM or a power grid issue you debugged across three tool domains. You know that place and route is not just about closing timing, it is about understanding the tradeoffs between power, performance, and area well enough to make the right call when all three are pulling in different directions. You are comfortable opening Fusion Compiler on Monday to close a complex hierarchical design and then jumping into PrimeTime or StarRC on Tuesday to figure out why a corner case is failing signoff. Real tape-out experience has taught you that the methodology matters as much as the result, and you care about building flows that do not just work once but scale across projects and teams. Working with foundries does not intimidate you. You have debugged enough DRC violations and worked through enough DTCO discussions to know how to translate between what a process team needs and what an implementation flow can actually deliver. You ask the right questions, push back when something does not make sense, and find a path forward without waiting for perfect clarity. At Synopsys, you will work directly with foundry partners and advanced node enablement teams on designs that define what is possible at the next process node.
What You'll Be Doing
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There are 632 open roles at Synopsys right now. This role centers on Place And Route, Fusion Compiler, Hierarchical Design, and Timing Closure.
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