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Senior Analog Design Engineer – Power & Clock IP
onsemi · Allen, TX · Posted 3 days ago
We are seeking a Senior Analog Design Engineer to develop power management and clocking IP for Treo-based SoCs. This role is a hands-on contributor expected to take ownership of complex analog blocks while collaborating across design, verification, and validation teams.
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This role centers on Analog Design, Power Management Ic, Clock Generation, and Soc Design. There are 715 open roles at onsemi right now.
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