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Senior Application Engineer (RTL-to-GDSII digital implementation)
Synopsys · Shanghai, Shanghai · Posted 3 days ago
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical implementation, running RTL-to-GDSII flows on designs that cannot afford to miss their PPA targets. You know that the difference between a CPU that tapes out on schedule and one that does not often comes down to a synthesis strategy chosen in week two or a floorplan decision that ripples through every subsequent stage. You have debugged enough timing violations and congestion hotspots to recognize patterns before they become problems. Working with high-performance compute designs excites you because the stakes are real and the constraints are unforgiving. You do not just run tools, you understand what is happening under the hood well enough to explain why a particular approach will or will not work for a customer's Arm CPU block at 3nm. When a customer hits a wall, you are the person who can sit with their data, reproduce the issue, and walk out with a path forward that their team can actually execute. You are comfortable being the bridge between a frustrated design team in Shanghai and an R&D engineer in Mountain View. You translate customer pain into requirements that make sense to product teams, and you turn new tool features into deployment strategies that customers trust. At Synopsys, you will work on the designs that power the next generation of processors, and the solutions you build will show up in silicon. What You'll Be Doing
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There are 632 open roles at Synopsys right now. This role centers on Rtl-to-gdsii, Synthesis, Place And Route, and Timing Closure.
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