Senior CPU Design Verification Engineer

We are seeking a Senior CPU Design Verification Engineer to own block‑ and subsystem‑level DV for advanced out‑of‑order (OoO) CPU cores . You will work closely with micro‑architects and RTL designers to verify complex Front end Designs includes branch prediction, Instruction decodes, execution pipelines, memory systems, and coherence protocols using modern, coverage‑driven methodologies.

Key Responsibilities

Verification Planning & Ownership

• • Drive verification for key OoO CPU blocks, such as:
• Front‑end: fetch, branch prediction, decode.
• Rename and register mapping.
• Issue queues / schedulers and execution units.
• Reorder buffer (ROB), retirement, exceptions, and flush/replay.
• Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences.
• L1 caches, TLBs, MMU interfaces, and coherence interfaces.
• Derive verification plans from architecture and micro‑architecture specs, with emphasis on:
• Speculative execution flows and pipeline hazards.
• Memory ordering / consistency model compliance.
• Interaction with cache hierarchy and coherence.

Testbench & Environment Development

• • Develop and maintain  SystemVerilog/UVM  testbenches:
• UVM agents, monitors, scoreboards, reference models.
• Constrained‑random stimulus and directed tests for OoO corner cases.
• Implement self‑checking mechanisms for:
• Instruction retirement and architectural state.
• LSU / memory ordering, atomics, and fence behavior.
• TLB, page‑table, and privilege/protection flows as needed.

Coverage & Quality

• Define and track  functional, code, and assertion coverage ; identify gaps and add tests/monitors to close them.
• Create and maintain  assertions (SVA)  for key micro‑architectural properties:
• No deadlock/livelock in scheduler, ROB, LSQ.
• Correct handling of mispredicts, exceptions, interrupts, and flush paths.
• Correct data forwarding and hazard resolution in the pipeline.
• Analyze regression results, triage failures, and drive issues to closure with design and architecture teams.

Debug & Collaboration

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