Senior Design Verification Engineer

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Job Summary:

Lattice Semiconductor is seeking a Senior Design Verification Engineer to join the Silicon team. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

Accountabilities

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
• Understand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
• Define and design verification regression environment
• Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
• Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
• Develop best practices and world class methods for SoC verification
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Required Skills

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