Senior Design Verification Engineer

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Responsibilities

• Lead verification of complex FPGA/ASIC IPs, subsystems, and SoC features from specification through tape-out.
• Develop verification strategies, test plans, and verification closure criteria aligned with product requirements.
• Architect and develop scalable SystemVerilog/UVM-based verification environments, checkers, assertions, scoreboards, and coverage models.
• Drive constrained-random and directed verification to achieve functional and code coverage goals.
• Debug design, testbench, simulation, and integration issues across RTL, GLS, low-power, and system-level verification environments.
• Collaborate closely with architects, design engineers, firmware engineers, and validation teams to ensure successful project execution.
• Drive verification sign-off activities, including coverage closure, regression analysis, and risk assessment.
• Mentor junior verification engineers and contribute to verification methodology improvements and reusable infrastructure.
• Support silicon bring-up and root-cause analysis when required.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
• 5+ years of experience in ASIC/FPGA functional verification.
• Strong expertise in SystemVerilog and UVM.
• Experience developing verification environments including drivers, monitors, scoreboards, assertions, and coverage models.
• Strong debugging skills across RTL, gate-level, and system-level simulations.
• Experience with industry-standard simulators and verification tools.
• Strong scripting skills in Python, Perl, Shell, or equivalent.

Preferred Qualifications

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