Senior DFT engineer

We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards.

Key Responsibilities a) Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration. b) Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures. c) Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings. d) Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability. e) Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage. f) Perform DFT verification, including verilog / gate level simulation g) Work closely with cross-functional teams to resolve DFT/testing timing challenges. i) Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness. j) Support silicon bring-up, production test debugging through Diagnostics and failure analysis.

Qualifications

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