Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)

Responsibilities

• Own verification planning and execution for Vector, ALU, floating-point blocks from testplanning to unit level verification and integration to core level.
• Drive verification strategy, test planning, Testbench development, tests writing, debug, coverage analysis, and closure for complex Vector, ALU, FPU execution-pipeline and datapath behaviours.
• Define effective verification approaches for arithmetic, floating-point, operand dependency, bypass/forwarding, replay, flush/recovery, exception, and execution-to-commit interactions.
• Develop robust verification environments, assertions, checkers, scoreboards, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
• Partner closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness.
• Drive efficient root-cause debug across specification, RTL, tests, and verification infrastructure.
• Contribute reusable methodology, automation, and infrastructure that improve verification quality and productivity across future CPU core programs.
• 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
• Strong hands-on experience with SystemVerilog, UVM -based verification and modern verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture.
• Experience verifying one or more of the following areas: ALU pipelines, floating-point execution, datapath verification, formal verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, debug, coverage analysis, and coverage closure.
• Good scripting or programming skills in Python, C/C++, or similar languages used for DV infrastructure and automation.

Preferred Qualifications

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