Senior Engineer - Design Verification

SiFive is looking for a Senior Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. This is a T3 / Senior Engineer individual-contributor role within the Interconnect horizontal area, focused on coherent interconnect and related subsystem behavior. In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interface types and bridge paths. We are looking for someone who can independently execute high-quality verification work, build robust environments, debug complex issues efficiently, and contribute to stronger verification methodology across the broader interconnect verification effort.

Responsibilities

• Understand the coherent interconnect architecture and create effective verification strategies and test plans for the assigned area.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, and error handling.
• Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including conversion, buffering, deinterleaving, and related data-movement behavior.
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, ordering, credits, arbitration, QoS behavior, and integration scenarios.
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Collaborate closely with architecture, design, formal, and software teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.
• 5+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in coherent interconnect, cache, memory-system, or CPU-subsystem verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and verification of ordering and flow-control semantics.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Experience verifying protocol behavior such as ordering, backpressure, buffering, arbitration, flow control, and error handling.
• Strong debugging skills and the ability to root-cause issues across specification, RTL, and verification environment layers.
• Strong problem-solving skills and the ability to work effectively across architecture, design, and verification teams.

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