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Senior Engineer - Hardware Engineering - DV
SiFive · Ahmedabad, Gujarat · Posted 5 days ago
Responsibilities:
- Hands on system Verilog/UVM development work for modern high performance CPU verification.
- Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification.
- Working with internal test generators to target coverage/test-plan scenarios.
Requirements:
- 3 years of experience in DV preferably in CPU verification.
- Proficiency in System Verilog and UVM methodology.
- Very good object-oriented programming skills.
- Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.
- Any scripting knowledge, preferably python.
- Bus interface knowledge like AXI or PCIE
- Integration experience with third party VIPs like bus VIPs.
- CPU micro-arch knowledge.
Additional Information:
This posting is sourced from SiFive's own career site — applying takes you there directly.
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There are 138 open roles at SiFive right now. This role is one of 394 Hardware Engineer openings and centers on Systemverilog, Uvm, Design Verification Experience (3 Years), and Object-oriented Programming.
See this month's Hiring Index: Fabs Are Closing. Design Isn't. for the broader trend behind roles like this one.
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