Senior OPC R&D Engineer

Job Description: As a lead OPC (Optical Proximity Correction) R&D Engineer, you will develop and implement, and guide other engineers in developing, high-quality technology solutions to optimize pattern fidelity, process window and reliability for critical memory patterning layers, using industry-standard software to model and correct for optical and other patterning effects, as well as employing DFM and RET solutions, ensuring that the final chip layout is accurately transferred to the wafer while meeting manufacturing requirements.Key Responsibilities:* OPC Solution Development: Drive development, implementation, and optimization of OPC models and recipes, including implementing appropriate advanced DFM and RET techniques, for critical memory layers. Lead patterning development with SMO studies, test plate design, and design rule evaluations.

• Tapeout Support: Validate OPC solution tapeout readiness and conduct quality reviews in conjunction with litho and process integration teams. Lead the patterning team to quickly resolve hotspot issues with effective data-driven solutions.
• OPC Performance Evaluation and Optimization: Work with development fab engineers to ensure the quality and performance of OPC solutions. Using validation and simulation software tools, guide effective wafer data collection for OPC verification to optimize mask quality, pattern fidelity and process window.
• Documentation and Training: Own creating documentation and training to help internal teams to understand and use the OPC tools and methodologies.
• Troubleshooting and Support: Provide technical support and guidance to internal teams who are using the OPC tools, helping them resolve issues and optimize their designs or processes.
• Collaboration and Communication: Collaborate closely with design rule, lithography, process integration, tapeout and mask engineering teams, to ensure that the OPC process is aligned with the overall chip manufacturing process.

…