Senior Silicon Validation Engineer

Location: Oxford, England, UK Working pattern: Hybrid

We are looking for a Senior Silicon Validation Engineer to join our Cryo-CMOS IC team at IonQ Oxford. You will lead the validation and characterisation of analogue and mixed-signal ASICs for our trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration.

This is a hands-on technical role. You will shape our validation architecture, build reusable hardware and software, and provide the evidence needed to make confident silicon acceptance decisions. The work includes room-temperature silicon validation and silicon characterisation at cryogenic temperatures (around 4 kelvin), on packaged parts, chip-on-board assemblies and bare die on a cryogenic probe station.

You will own validation delivery across chip and system interfaces, working closely with analogue and digital design, verification, modelling, firmware and systems engineers. You will turn requirements into measurable tests, prepare platforms before silicon arrives and resolve failures across the chip, board and software.

As a Senior engineer, you will set technical standards, guide other engineers and improve coverage, repeatability and test efficiency across successive ASIC generations.

Key responsibilities include:

• Own the silicon validation strategy, plans, acceptance criteria and readiness reviews, with traceability from block and system requirements to tests, results and unresolved risks.

• Present the silicon acceptance report to the Cryo-CMOS IC Lead and programme stakeholders.

• Lead first-silicon bring-up and characterisation of sample-and-hold and switch arrays, DACs, ADCs, references, amplifiers, switches, regulators, clocking and device-level test structures, across supply, temperature, operating modes and device variation, with sound calibration and measurement uncertainty.

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