Senior Staff AI Accelerator Performance Architect

SENIOR STAFF AI ACCELERATOR PERFORMANCE ARCHITECT

Wafer-scale computing creates a distinctive architecture space in which compute placement, memory capacity and bandwidth, communication, kernel execution and system-level behavior must be understood together.

We are looking for a performance architect to guide the evolution of our next-generation AI systems. You will connect real workloads to architectural behavior, identify the bottlenecks that matter, quantify potential improvements and influence hardware and software roadmaps through rigorous performance analysis.

This role is ideal for someone with deep knowledge of hardware architecture, developed through hardware, compiler, kernel or system-performance work, who enjoys operating at the intersection of applications, kernels, architecture and system performance.

• Own and evolve performance models and modeling methodologies for next-generation accelerator and system architectures.
• Build and extend analytical, simulation-based or trace-driven models across workloads, architectural features and product generations.
• Analyze important AI workloads, from individual kernels through end-to-end inference and training execution, to determine where time, bandwidth, compute and capacity are spent.
• Identify hardware and software bottlenecks and quantify opportunities to improve latency, throughput, utilization and energy efficiency.
• Evaluate proposed architectural features and determine their expected performance return across representative workloads.
• Study how models and kernels map onto the underlying compute, memory and communication architecture.
• Partner with architecture, compiler, kernel, runtime and systems teams to evaluate alternative mappings and optimizations.
• Develop workload projections and competitive performance analyses grounded in transparent assumptions.
• Create concise recommendations that translate complex performance results into architectural and product decisions.
• Improve modeling methodology, validation and correlation with RTL, emulation and silicon measurements.
• Help define representative workloads, performance targets and success criteria for future products.

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