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Senior System Power Architect
Lattice Semiconductor · San Jose, CA · Posted 6 days ago
Job Description: Senior System Power Architect
The Senior System Power Architect drives power analysis and low-power optimization across Lattice FPGA hardware and software. The role involves the design of low-power feature specifications, algorithms, and methodology, collaborating with hardware, software, marketing, and applications teams.
- Define low-power feature specifications, user flows, algorithms, and align software, marketing, and applications teams
- Drive power-performance analysis to influence hardware and software roadmaps
- Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O, and correlate models with simulations and silicon
- Establish power-aware RTL methodology
- Develop power and competitive benchmarks
- Lead and mentor junior engineers across distributed teams
- BS/MS/PhD in EE, CE, CS, or related field with 8+/6+/3+ years of relevant experience
- Strong knowledge of low-power design techniques
- Deep expertise in RTL and gate-level power analysis and optimization, as well as power-aware synthesis and P&R
- Hands-on experience with industry power/timing tools (e.g., PrimePower, PrimeTime, SpyGlass, Joules, Voltus, PowerArtist) with strong knowledge of STA, and power/timing ECO flows
- Proficiency in C/C++ and Python
- Strong written and verbal communication skills
- Ability to drive cross-functional alignment
- Knowledge of FPGA architecture, design flows, and use cases is strongly preferred
Base Pay Range 220,000.00 In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information:
This posting is sourced from Lattice Semiconductor's own career site — applying takes you there directly.
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