Senior Technical Manager, Memory Innovations

Lead groundbreaking memory technologies at TSMC Design Technology Canada Inc. as a Senior Technical Manager focused on Design for Test and Memory BIST. This pivotal role demands engineering excellence and innovation. As a Senior Technical Manager in Ottawa, you'll take control of DFT architecture while tackling unprecedented challenges in memory technology.

You'll leverage over 10 years of specialized experience in memory testing, self-testing development, and advanced algorithms. Collaboration with global teams ensures the development of cutting-edge, energy-efficient solutions. Key Responsibilities:

Define and govern Memory BIST DFT architectural strategiesDevelop innovative BIST engines for advanced memory typesConduct robust fault modeling and debugging to enhance qualityImplement memory-specific DFT solutions for complex designsLead EDA tool interactions and negotiate with vendors Requirements:10+ years in memory test and self-test developmentExpertise in memory defect modeling and failure analysisStrong understanding of EDA tools like Synopsys and CadenceProficient in ASIC design and chip integration techniquesProblem-solving skills for undefined memory challenges Shape the future of memory technologies at TSMC through innovative test solutions and advanced design methodologies.