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Sr Director, XSE Design Verification Engineering Manager

Intel · Santa Clara, CA · Posted 7 days ago

$256k–$361kdir
12+ yrs expSoC design verificationASIC design verificationSilicon design verificationMicroarchitecturePost-silicon validationHardware emulationIndustry-standard protocolsSecurity validation

"Lead a team of design verification engineers on Intel's next-generation Xeon SoCs for the data center, partnering with architecture and post-silicon teams."

Job Description: The Role and Impact As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible for Xeon SoC design verification. You will deploys and manage leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. You will work with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. You will also bring a culture of rapid execution with high quality and simplify complicated process flows. This critical role ensures delivery excellence, directly contributing to Intel's broader success in creating innovative technology solutions.

Business group The Data Center Group (DCG) is at the forefront of Intel's mission to deliver advanced technologies that power cloud computing, enterprise, AI, and edge solutions. Within DCG, the DSE Xeon SoC Engineering organization specializes in developing cutting-edge SoC designs to drive next-generation data center performance. Joining this team means being part of a collaborative environment dedicated to shaping the future of data-driven innovation.

Key Responsibilities

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Related roles

There are 928 open roles at Intel right now. This role is one of 18 Engineering Manager openings in Santa Clara, CA and centers on Soc Design Verification, Asic Design Verification, Industry-standard Protocols, and AI.

See this month's Hiring Index: Fabs Are Closing. Design Isn't. for the broader trend behind roles like this one.

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