Sr. Staff Design Engineer

Job Description: Duties:

Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.

This role involves:

• Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
• Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
• Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
• Analyzing hardware capabilities and contributing to customer solution strategies.
• Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
• Collaborating cross-functionally with software and applications teams to communicate requirements, resolve issues, and drive enhancements.

Specific duties include:

• Architect and develop DDR Memory Controller soft IPs
• Optimize soft IPs to achieve better performance (latency, size, frequency)
• FPGA design and implementation using software primitives
• Integration with third-party hardened PHYs
• Team leadership and stakeholder management
• Static Timing Analysis (STA) and constraint writing
• RISC-V based system design and evaluation
• Customer support and issue resolution
• Quality review of third-party deliverables
• Test development to validate implementation and ensure high quality

Minimum Requirements:

• Bachelor’s degree in Electronics Engineering, Applied Physics or related field
• 8 years of experience as Design Engineer or related field

Prior experience to include:

• FPGA and SoC ASIC development.
• IP for FPGA and ASIC products
• FPGA RTL design, logic verification, debug and timing closure
• DDR protocols (e.g.: DDR3, DDR4, LPDDR4, DDR5)
• High-speed interface subsystems
• High-speed protocols (PCIe, Ethernet, and MIPI)
• Peripheral IPs (UART, SPI, I2C, and I3C)
• Hardware validation and hardware interoperability testing

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