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Sr. Staff Engineer - Design Formal Verification
SiFive · Hyderabad, Telangana · Posted 5 days ago
Own formal verification strategy for complex processor modules like instruction fetch, branch prediction, and execution pipelines, while guiding and training a team.
As a Senior Staff Hardware Engineer in Design formal Verification, you will own and drive the strategies to verify complex modules under different functional domains like instruction fetch, branch predictions, Instruction execution pipelines etc.
Responsibilities:
- Identify blocks suitable for applying Formal Verification
- Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
- Implementation and maintenance of Formal Verification environments in Chisel
- Applying various FV techniques to reduce complexity and prove correctness of DUT
- Debugging RTL to identify causes of failure scenarios
- Guide and train team members on effective usage of Formal Verification tools
- Develop/modify scripts to automate the verification process
- Review formal setups and proofs with design and verification teams
- Maintain and extend assertion libraries
Requirements:
- 10+ years of experience in Formal Verification of Digital Hardware Design
- Extensive experience with Formal Abstraction Techniques and sign-off process
- Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold
- Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog
- Knowledge of Object-oriented Programming is a plus
- A keen interest in Processors and Digital systems
- Strong reasoning skills and excellent attention to detail
- Good inter-personal and teamwork skills!
Additional Information:
This posting is sourced from SiFive's own career site — applying takes you there directly.
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There are 138 open roles at SiFive right now. This role centers on Formal Verification, Formal Abstraction Techniques, Vc Formal, and Jaspergold.
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