Sr Staff Engineer-DFT

Your Team, Your Impact

Marvell’s Optical DSP (ODSP) team within the Connectivity Business Unit develops advanced, industry-leading ASICs for the hyperscale data center, enterprise, and AI infrastructure markets. Our products — including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers — are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. The ODSP team operates at the leading edge of semiconductor technology, developing chips in TSMC advanced process nodes. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina — and we are looking for a senior staff DFT engineer in Santa Clara on our next-generation ODSP program, to help set up the methodology and flow on our flagship products. What You Can Expect

• Define DFT architecture and implementation for a block within the chip, including hierarchical DFT, test modes and clocking.
• Plan, partition and integrate IP-level DFT (SerDes, PLL, memories, third-party IP).
• Drive ATPG coverage, test-time and pattern-count targets; optimize compression and power during test.
• Lead DFT sign-off: DRC, simulation, timing, equivalence, and handoff to PD/ATE.
• Debug silicon: failure isolation, diagnosis, yield learning with Product/Test engineering.
• Mentor junior engineers; review their work; coordinate with design, verification, PD, and test.
• Improve methodology and automation.

What We're Looking For

• BS in EE/CE with 8+ years or MS in EE/CE with 5+ years of DFT experience on complex SoCs, with multiple tape-outs and silicon bring-ups
• Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed test.
• Strong DFT timing/STA knowledge; experience with advanced nodes (7nm and below preferred).
• Proven independent problem solving and mentoring.
• Experience with high-speed SerDes/DSP products is a plus.

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