Sr. Staff Engineer, IP Runtime

You will work at the hardware/software boundary to define how those hardware blocks are initialized, coordinated, and used by the runtime. You will determine how workloads are dispatched, scheduled, synchronized, and executed across the accelerator, while solving complex performance problems through implementation, bring-up, and debugging.

This role is hybrid and based in Toronto, ON or Austin, TX.

• An expert C or C++ engineer with a track record of designing and delivering complex, performance-critical systems.
• Experienced working close to hardware in low-level, embedded, bare-metal, or accelerator environments and translating hardware specifications into reliable software behavior.
• Strong in runtime fundamentals, including command execution, scheduling, synchronization, memory movement, resource management, and parallelism.
• Skilled at debugging and optimizing systems end-to-end, especially at the hardware/software boundary.
• A technical leader who collaborates effectively across hardware, firmware, compiler, and systems teams and mentors other engineers.
• Define the runtime architecture and implementation that controls execution, scheduling, synchronization, and resource management across Tenstorrent’s custom processor, accelerator, memory, and data-movement IP.
• Build low-level runtime components that initialize hardware IP, dispatch work to processor and accelerator engines, coordinate dependencies, and manage resources efficiently.
• Design runtime interfaces and data-movement paths that make memory access, synchronization, and execution efficient and predictable.
• Analyze bottlenecks across the runtime and hardware/software stack, then drive improvements in latency, throughput, scalability, and reliability.
• Influence the direction of the runtime stack, engage directly with customers and field-facing teams, and translate real-world workload needs into runtime improvements while remaining hands-on with design, coding, performance analysis, bring-up, and debugging.
• How runtime software exposes and controls custom silicon IP, from hardware initialization and execution control through bring-up, performance analysis, and optimization.
• How custom silicon IP blocks—including RISC-V processor cores, accelerator engines, memory systems, data-movement logic, and interconnects—work together as a complete execution platform.
• Advanced techniques for execution control, synchronization, scheduling, and performance optimization on massively parallel hardware.
• How runtime and hardware co-evolve to improve model throughput, efficiency, and scalability.