Staff CPU Design Verification Engineer

As a Staff Hardware Engineer in Design Verification of CPU, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems . You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out.

Key Responsibilities

Verification Ownership

• Own verification of  OOO core subsystems , e.g.:
• Front‑end: fetch, branch prediction, instruction decode, rename.
• Back‑end: scheduler/issue queues, execution units, bypass networks.
• Retirement & recovery: ROB, commit, exceptions, interrupts, mispredict recovery.
• Good knowledge on execution pipelines and multiple execution pipeline scenarios.
• Memory subsystem: LSU, TLBs, MMU, L1/L2 caches, coherence, fences, atomics.
• Define verification strategy and test plans from  ISA + micro‑architecture specs , with emphasis on:
• Speculative execution, forwarding, hazards, and replay mechanisms.
• Memory consistency model (e.g. RVWMO, TSO) and ordering rules.
• Coherence/consistency interactions across multi‑core systems.
• Drive coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria.

Testbench Architecture & Implementation

• Architect constrained‑random, coverage‑driven UVM testbenches for:
• OOO core pipeline (including scoreboards and scoreboard‑driven checking).
• Cache/memory hierarchy, TLB/IOMMU, and coherence protocols.
• Develop reusable verification components: generators for  OOO stress  (back‑to‑back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.
• Model reference behavior (ISA / memory model) for end‑to‑end checking of:
• Instruction retirement,
• Register and memory architectural state,
• Fence and atomic semantics.

Formal & Assertion‑based Verification

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