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Staff Design Engineer
Lattice Semiconductor · Penang, Malaysia · Posted today
Own USB controller and PHY integration for next-generation FPGA products, from subsystem RTL and validation through silicon bring-up and customer issue resolution.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Position Summary Join the winning team! Lattice is looking for a motivated and experienced Staff Design Engineer to integrate and productize USB IP and subsystems for next-generation FPGA products. The role focuses on USB 2.0 and USB 3.x controller and PHY integration, spanning subsystem validation, software enablement, silicon bring-up, and collaboration across Design, DV, Software, Applications, and external IP partners.
Key Responsibilities
- Own the integration of USB controller and USB PHY IP into the FPGA subsystem, including digital interfaces, configuration paths, clock/reset connectivity, and integration requirements.
- Define and implement the subsystem-level RTL, wrappers, adapters, control logic, and configuration interfaces required to integrate USB controller and PHY IP.
- Work with Design Verification teams to define integration test plans and validate end-to-end USB subsystem behavior through simulation, emulation, FPGA prototyping, coverage closure, and pre-silicon debug.
- Drive subsystem-level root-cause analysis across USB controller-to-PHY interaction, integration RTL, software or firmware configuration, interoperability, compliance, and silicon behavior.
- Work with software and firmware teams to define and validate USB configuration, feature enablement, diagnostics, enumeration, initialization, and user-flow requirements.
- Integrate and review DFT and DFD requirements for the USB subsystem, including testability, debug observability, silicon bring-up, and production-test considerations.
- Work with third-party suppliers of USB controller and PHY IP to clarify interface and configuration requirements, review deliverables, and resolve integration, verification, and silicon issues.
- Develop and maintain USB subsystem integration specifications, interface requirements, configuration documentation, and bring-up guidelines.
- Support integrated USB subsystem bring-up, laboratory debug, protocol analysis, compliance and interoperability testing, and customer issue resolution; document findings and drive assigned issues to closure.
- Identify engineering activities that can benefit from AI assistance, and propose, develop, and deploy practical AI-assisted workflows for design, verification, debug, data analysis, and technical documentation.
- Participate in design reviews and quality checks, and contribute to continuous improvement of design and debug methodologies.
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There are 162 open roles at Lattice Semiconductor right now. This role centers on Rtl Design, Usb 2.0, Usb 3.x, and Clock/reset Architecture.
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