Staff Design Verification Engineer

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description: Responsibilities

• Lead verification planning, execution, and sign-off for complex FPGA/ASIC IPs, subsystems, and SoC-level designs.
• Define verification methodologies, test strategies, coverage goals, and closure criteria for project deliverables.
• Architect and develop advanced SystemVerilog/UVM verification environments, reusable verification components, scoreboards, assertions, and coverage models.
• Drive verification closure through functional coverage, code coverage, regression analysis, and risk assessments.
• Lead debug of complex RTL, integration, low-power, timing, and gate-level simulation issues.
• Collaborate with architects, RTL designers, validation engineers, firmware teams, and program managers to ensure successful product execution.
• Provide technical leadership for verification methodologies, automation, infrastructure, and best practices across projects.
• Mentor and guide verification engineers, perform design and verification reviews, and drive team technical excellence.
• Support silicon bring-up, failure analysis, and root-cause investigations as required.
• Drive continuous improvements in verification productivity, quality, and reusability.

Required Qualifications

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