Staff EDA Engineer

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Job Description:

Lattice is seeking a Senior CAD/EDA Engineer with deep expertise in Static Timing Analysis (STA), Place and Route (PNR), and hierarchical timing abstraction using Extracted Timing Models (ETM) and Quick Timing Models (QTM), to join our CAD/EDA Engineering group in Pune, India. Qualified candidates must hold a BS or MS degree in EE, ECE, or CoE with 8 to 12 years of industry experience on 5, 7, 16, or 28 nm process technology nodes. This individual will be a key driver in developing, deploying, and supporting the logic and digital design implementation and signoff methodologies and flows across the company's FPGA product lines

The candidate's general responsibilities include the following: Static Timing Analysis and Signoff

• Own and maintain the multi-corner multi-mode (MCMM) STA signoff methodology, including constraint development, timing closure criteria, and signoff sign-check automation.
• Develop and support timing signoff flows using Synopsys PrimeTime, PrimeTime SI, and Cadence Tempus, covering setup, hold, recovery/removal, and transition/capacitance checks.
• Deploy advanced variation modeling methodologies including AOCV, POCV, and LVF, and define derating and margining strategies across process nodes.
• Drive crosstalk and signal integrity analysis, noise-aware timing, and correlation between implementation and signoff timing engines.
• Define and automate SDC generation, validation, and equivalence checking across RTL, synthesis, PNR, and signoff stages.

Timing Abstraction: ETM and QTM

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