Staff Engineer, RTL Design, AI Hardware

You’ll join Tenstorrent’s AI Hardware team in Belgrade, building the silicon behind Tenstorrent’s custom AI platform. As a Staff RTL Design Engineer, you will contribute to the development of next-generation AI hardware by implementing and optimizing micro-architectures, improving performance and power efficiency, and collaborating across hardware teams. This role offers the opportunity to work on challenging, high-impact designs in a fast-paced environment.

This role is hybrid, based out of Belgrade, Serbia.

• An engineer with a demonstrated depth in digital design and micro-architecture, and ability to make architectural decisions and solve novel problems with broad downstream impact..
• Demonstrated hands-on expertise and ownership of complex designs through RTL, verification, implementation, and silicon or post-silicon debug where applicable.
• Comfortable writing Verilog or SystemVerilog and interpreting synthesis and timing results.
• Track record of delivering complex ASIC or accelerator hardware, with experience in providing technical direction, mentoring engineers and raising design quality across the team.
• Engineers who own a coherent technical area or subsystem, implement and refine its micro-architectural features, influence its architecture and interfaces, and guide related implementation work across multiple contributors or teams.
• Lead complex PPA trade-offs, make recommendations adopted across teams, and own the resulting technical outcome while balancing power, area, and frequency.
• Drive alignment across RTL, DV, performance, physical design, software, and architecture, resolve interface or dependency conflicts, and establish a clear technical path forward.
• Identify ambiguous or novel failure modes, coordinate root-cause analysis across teams, anticipate downstream impact, and drive corrective action through validation closure
• Provide technical direction and mentorship to engineers, establish reusable design practices, review standards, and methodologies that improve quality and execution, and represent the team in architecture and cross-functional reviews, clearly communicating trade-offs, risks, and recommendations.
• Techniques for developing high-performance RTL targeting AI and ML workloads.
• How power, performance, and area are balanced across design, verification, and physical implementation.
• Tools and methods used to evaluate design trade-offs and optimize compute architectures.
• What it takes to ship production-grade silicon that supports next-generation AI systems.