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Staff Engineer
SiFive · Bengaluru, Karnataka · Posted 5 days ago
ic
7+ yrs expSystemVerilogUVMRISC-VPythonAXIPCIeCPU verificationObject-oriented programming
Responsibilities:
- Hands on system Verilog/UVM development work for modern high performance CPU verification.
- Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification.
- Working with internal test generators to target coverage/test-plan scenarios.
Requirements:
- 7-12 years of experience in DV preferably in CPU verification with a bachelor's or master's degree.
- Proficiency in System Verilog and UVM methodology.
- Very good object-oriented programming skills.
- Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.
- Any scripting knowledge, preferably python.
- Bus interface knowledge like AXI or PCIE
- Integration experience with third party VIPs like bus VIPs.
- CPU micro-arch knowledge.
Additional Information:
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This role centers on Systemverilog, Uvm, Object-oriented Programming, and Cpu Architecture (x86, Arm, Or Risc-v). There are 138 open roles at SiFive right now.
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