Staff Physical Design Engineer: CPU Implementation & Flow Automation

The Role: As a Staff Physical Design Engineer , you will be responsible for developing and perfecting the RTL-to-GDS implementation flow for our high-performance CPU cores. You will take ownership of advanced implementation recipes, driving PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This role combines deep technical execution with the development of automated, ML-enhanced methodologies to ensure our CPU designs hit aggressive frequency and power targets.

Key Responsibilities

• Flow Development & Execution: Develop, validate, and deploy production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler
• PPA Optimization: Drive block-level and hierarchical PPA closure, utilizing advanced techniques in timing-driven placement, CTS, and routing.
• ML Implementation: Hands-on deployment of ML optimization tools (DSO.ai) to automate design space exploration and achieve optimal PPA results.
• Technical Support: Serve as the first line of defense for flow and tool-related issues, working closely with the methodology team to resolve bottlenecks.
• Collaboration: Partner with IP teams (SRAM/Std Cell) to characterize and model PPA impacts on the overall flow.
• Automation: Create and maintain robust Tcl/Python scripts to improve flow efficiency and ensure repeatable, predictable results across design iterations.

Requirements

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