Staff Verification Engineer - Security Blocks

Core Responsibilities

• Verification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.
• Testbench Development: Design and implement scalable, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Stimulus & Constraint Generation: Write complex sequences and constrained-random tests to stress-test the IP across corner cases.
• Debugging: Perform deep-dive root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).
• Coverage Closure: Define and track functional and code coverage metrics. Write covergroups and coverpoints to ensure all architectural features have been exercised.
• Must know the RISC-V spec and processor-based verification and knowing risc-v security architecture is highly preferable.
• Languages    : SystemVerilog, Verilog, Python/Perl (scripting), C/C++
• Methodologies    UVM (highly preferred), OVM, or VMM
• Protocols    AXI,   AHB, Security architecture

Requirements:

• 7-12 years of experience in DV preferably in CPU verification with a Bachelor’s or Master’s in Engineering
• Proficiency in System Verilog and UVM methodology.
• Very good object-oriented programming skills.
• Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience.
• Any scripting knowledge, preferably python.
• Bus interface knowledge like AXI or PCIE
• Integration experience with third party VIPs like bus VIPs.
• CPU micro-arch knowledge.

Additional Information: