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Standard Cell / GPIO Design Engineer (2 nm Technology Node)
Rapidus Corporation · Albany, NY · Posted 115 days ago
Job Title: Standard Cell / GPIO Design Engineer (2 nm Technology Node) Team: Enablement / Foundation IP Development
Location: Albany (NY), Santa Clara (CA), or Tokyo (Japan)
Overview Rapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond. We are seeking skilled engineers to join our Foundation IP Design Team , focusing on Standard Cell and GPIO (General Purpose I/O) development.
Engineers with expertise in circuit design, layout, reliability, or DTCO are all welcome.
This position involves close collaboration with process, device, and enablement teams to deliver high-quality, high-performance IP that supports leading-edge logic technologies.
About Rapidus Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry. Why Join Us You will play a central leadership role in building the world’s most advanced 2nm and next ‑ generation enablement ecosystem , shaping the foundation for future semiconductor innovation. You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)
Key Responsibilities
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This posting is sourced from Rapidus Corporation's own career site — applying takes you there directly.
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There are 20 open roles at Rapidus Corporation right now. This role centers on Standard Cell Design, I/o Circuit Design, Custom Circuit Design, and Cmos Device Behavior.
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