Tech Lead, Asic Design

Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

• RTL Design & Implementation
• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
• Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
• Cross-Functional Execution
• Partner with architecture to translate specifications into implementation-ready microarchitecture
• Collaborate with verification on testplans, coverage closure, and bug triage
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
• Technical Leadership & Quality
• Mentor junior engineers and contribute to design methodology, scripts, and best practices
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
• Drive structured, data-driven design decisions in support of aggressive tapeout schedules

Basic Qualifications

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